1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to priority encoding circuitry for use in an integrated circuit microprocessor.
2. Description of the Prior Art
Recent improvements in MOS semiconductor technology have resulted in advances in large scale integrated circuit microprocessors. Current LSI microprocessors are an order of magnitude more powerful than the previous generation introduced three or four years ago. The latest generation of microprocessors have 16 bit data paths, 16 bit arithmetic capability, and they directly address multiplemegabyte memories. In terms of functional capability and speed, they will out perform all but the high end models of current 16 bit minicomputers. LSI microprocessor design is now at a stage where better implementation techniques are required in order to control complexity and meet tighter design specifications.
As is well known, data processing systems including microprocessors are generally equipped with various data and address registers which either temporarily store information which is to be transferred to memory in a WRITE mode or which receive information from memory in a READ mode. In some instances, it is necessary to store information into or extract information from selected ones of this plurality of registers in accordance with some predefined priority scheme. For example, the MC68000 microprocessor chip generally available from Motorola, Inc. utilizes a "load and store multiple" instruction which cause information stored in various data registers in the microprocessor to be stored into memory or, on the other hand, which causes information in memory to be read into specific ones of these registers. For this purpose, a multi-bit word is constructed within the microprocessor which indicates which registers are to be manipulated and in what priority. For example, if each of the individual bits of a data word represent separate and distinct registers, then a logic one in any particular bit position will indicate that its associated register is to be either read into or read from. Furthermore, the relative priority of operations associated with any one particular register with respect to the others may be determined by the relative position of its associated bit in the data word. Thus, for example, a register whose associated bit position occupies the least significant bit of the data word may be given highest priority while one associated with the most significant bit position may be given the lowest priority. It is necessary, however, to monitor each of the bit positions in order to detect the bit position of highest priority containing a logic one so as to perform the required operation on its associated register, the bit position containing a logic one of next highest priority in order to perform the required operation on its associated register and so on down the line until the correct operation has been performed on each register whose associated bit in the data word is a logical one.
Two approaches are known for providing the proper priority encoding. First, a decoding circuit may be coupled to each of the bits in the data register word and determine therefrom which register is to be operated on first in accordance with what bits are occupied by logical ones and the relative positions of these bits within the data register word. Once the operation on the register of highest priority has been completed, the decoder must be capable of detecting the register with the second highest priority, then the register with the third highest priority and so on. It should be clear that such a decoding circuit would be of necessity very complex. This would not only require a great deal of silicon area on the integrated circuit chip but which would also increase the power requirements of the chip.
A second known approach is to utilize a digital counter which cycles through a series of counts equivalent to the number of bits in the data register word. For example, during count 1 of the digital counter, bit one of the data register word would be sampled in order to determine if it contained a logical one. If it did, the appropriate operation would be performed on its associated register and the counter would then increment by one count. The next bit in the data register word would then be sampled to determine its contents. This process would continue until each of the bits in the data register word was examined and all operations on the associated registers completed. It should be clear that this technique suffers from the disadvantage of unwanted delays incurred during examination of data registers bits which include a zero indicating that no operation is to be performed on its associated register. These unnecessary delays reduce the overall speed capability of the microprocessor.